PCI Express bus has been evolving for over ten years now. So far the technology has tripled its initial data rate, but the next step is taking a longer time. PCI SIG claims that the fourth generation PCI Express specification will be finalized in 2017 and will materialize this decade. The new tech will use a new connector and will be the last copper version of PCI Express.
The PCI SIG [special interest group] has been developing PCI Express 4.0 since late 2011. The target data rate of the new bus is 16GT/s [gigatransfers per second] per lane and the organization has consistently set this target even though many did not believe that it was viable using a wide bus with copper interconnects. The standard is still not finalized because participants have to agree on a number of parameters, including interconnect attributes, fabric management as well as programming interface required to design and build systems and peripherals that are compliant with the PCI Express 4.0 specification.
For example, so far the PCI SIG has not agreed on the maximum length of PCIe 4.0 traces without retimers. Many applications, such as servers and communications equipment, need longer interconnections.
“We are getting 16GT/s, something no one thought was possible a few years ago,” said Al Yanes, president of the PCI SIG, in an interview with EE Times. “The base distance is still being validated but it’s typically 7 inches or so. Longer channels of 15 inches or so with two connectors will have retimers, but Gen 3 has used retimers – now we will need to use them for shorter long channels.”
PCI Express 4.0 will utilize a new connector, but the specification will be backward compatible mechanically and electrically with PCI Express 3.0, which means that it will be possible to use today’s add-in-cards in PCIe 4.0-based systems, but future AICs will not work with PCIe 3.0.
“We’ve done a lot of analysis on the connector – we tried everything possible,” said Mr. Yanes. “We have some top engineers in our electrical work group and they’ve come through – its exciting to see the amount of activity and participation.”
16GT/s base transfer rate will allow PCI Express 4.0 x1 interconnection to transfer up to 2GB of data per second, whereas the PCIe 4.0 x16 slots used for graphics cards and ultra-high-end solid-state drives will provide up to 32GB/s of bandwidth. Higher transfer rates will also let mobile devices to save power since it will take less time to transfer data.
At present Al Yanes believes that fifth-generation PCI Express will have to rely on optical, not copper links. This means a major change, which will happen sometimes in the next decade. Keeping in mind that bandwidth is a major factor that limits performance of supercomputers, PCI Express standard featuring optical links could emerge rather sooner than later.
“I got to believe engineers will find way to make [optics] cost effective by the time they are needed – even four years ago there was a big push on it,” said the head of the PCI SIG.
Developers at the PCI SIG hope to release PCI Express 4 version 0.7 specification this year, but the technology will be finalized only by 2017