作者: kaidai 時間: 2021-11-23 19:12 標題: Intel 12th + DDR4 得 one channel ?
https://edc.intel.com/content/ww ... mory-controller-mc/
系我理解錯誤，定點樣?
作者: nelsonlee130 時間: 2021-11-23 19:16
There are two instances of MC, one per memory slice.
作者: kaidai 時間: 2021-11-23 19:46
回覆 2# nelsonlee130
one per memory slice 系指
1. 每種DDR 技術 有兩個memory controller ，定係
2. DDR4 及 DDR5 各有1個memory controller
作者: nelsonlee130 時間: 2021-11-23 19:53
咁你諗住點演繹下一句...
Each controller is capable of supporting up to two channels of DDR5 and one channel of DDR4.
作者: kaidai 時間: 2021-11-23 20:00
每一個memory controller 分別支援兩channelDDR5 及 1channelDDR4
作者: nelsonlee130 時間: 2021-11-23 20:05
繼續睇落去？
The two controllers are independent and have no means of communicating with each other, they need to be configured separately.
In a symmetric memory population, each controller only view half of the total physical memory address space.
作者: kaidai 時間: 2021-11-23 20:09
回覆 6# nelsonlee130
唉，我就系唔明先問?
作者: finepix 時間: 2021-11-23 21:21
回覆 8# finepix
睇呢幅圖應該易明D.
