[中央處理器] Intel 12th + DDR4 得 one channel ?

kaidai

https://edc.intel.com/content/ww ... mory-controller-mc/

系我理解錯誤，定點樣?

nelsonlee130

There are two instances of MC, one per memory slice.

kaidai

回覆 2# nelsonlee130

one per memory slice 系指
1. 每種DDR 技術 有兩個memory controller ，定係
2. DDR4 及 DDR5 各有1個memory controller

nelsonlee130

咁你諗住點演繹下一句...

Each controller is capable of supporting up to two channels of DDR5 and one channel of DDR4.

kaidai

每一個memory controller 分別支援兩channelDDR5 及 1channelDDR4

nelsonlee130

繼續睇落去？

The two controllers are independent and have no means of communicating with each other, they need to be configured separately.

In a symmetric memory population, each controller only view half of the total physical memory address space.

kaidai

回覆 6# nelsonlee130

唉，我就系唔明先問?

finepix

回覆 8# finepix

睇呢幅圖應該易明D.