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kaidai

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tT
發表於 2021-11-23 19:12 | 只看該作者

[中央處理器] Intel 12th + DDR4 得 one channel ?

https://edc.intel.com/content/ww ... mory-controller-mc/

系我理解錯誤，定點樣?
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finepix

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8#
發表於 2021-11-23 21:21 | 只看該作者
回覆 8# finepix

睇呢幅圖應該易明D.

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kaidai

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7#
發表於 2021-11-23 20:09 | 只看該作者
回覆 6# nelsonlee130

唉，我就系唔明先問?

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nelsonlee130

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6#
發表於 2021-11-23 20:05 | 只看該作者
繼續睇落去？

The two controllers are independent and have no means of communicating with each other, they need to be configured separately.

In a symmetric memory population, each controller only view half of the total physical memory address space.

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kaidai

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5#
發表於 2021-11-23 20:00 | 只看該作者
每一個memory controller 分別支援兩channelDDR5 及 1channelDDR4

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nelsonlee130

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4#
發表於 2021-11-23 19:53 | 只看該作者
咁你諗住點演繹下一句...

Each controller is capable of supporting up to two channels of DDR5 and one channel of DDR4.

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kaidai

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3#
發表於 2021-11-23 19:46 | 只看該作者
回覆 2# nelsonlee130

one per memory slice 系指
1. 每種DDR 技術 有兩個memory controller ，定係
2. DDR4 及 DDR5 各有1個memory controller

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nelsonlee130

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2#
發表於 2021-11-23 19:16 | 只看該作者
There are two instances of MC, one per memory slice.

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