Mygica D689 status update

Tonight, I tried at living room which the wall plug has a better signal.
D689 can play both 482MHz and 586MHz.
can log 602MHz with bit error, same result as my MagicTV set-top box.

So I think it is about signal strength, with same code, I still have problem at my bedroom.

I made a bit modification on the code, I will push it to my repository later for your reference,
but I don't think they matter.

Thanks in advanced
I asked Altobeam sometime ago about the driver
their reply was:

We do have a Linux version driver, but it is not commercially released. I will check with our SW team to determine whether we can release a beta version through Mygica website.  

Looks like we now have an open source solution
How did you make it
lots of thanks

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原帖由 Ice_cube 於 2009-11-24 00:24 發表
Thanks in advanced
I asked Altobeam sometime ago about the driver
their reply was:

We do have a Linux version driver, but it is not commercially released. I will check with our SW  ...


Indeed, I work with the hardware design house behind Mygica....
They gave me information for this volunteer work.

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i have two cards, one is 8506 and the other is 689. my 8506 can scan all 11 stations ok, but the 689 scans nothing. so i think the signal strength is a problem but not the only problem. please release your new version of driver, if possible, please share the spec doc of the 8831.

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回覆 1# 的帖子

多謝曬 David 兄, update 左請通知一下

EDIT:
原來 update 左了, Thanks. 夜D 試一下

[ 本帖最後由 netter 於 2009-11-24 11:58 編輯 ]

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原帖由 chancho 於 2009-11-24 11:25 發表
i have two cards, one is 8506 and the other is 689. my 8506 can scan all 11 stations ok, but the 689 scans nothing. so i think the signal strength is a problem but not the only problem. please release ...


I agree that D689 not performs as good as LGS8GL5, but please try with a better signal.
The signal at my home is marginal, even set-top box can't lock 602MHz, so results at my
home doesn't tell much. However, I think I have done my best and I guess I can't help more.
Perhaps logging more Windows driver activities may help.

The 8830 documents are under Non-Disclosure Agreement with hardware vendor.
I really cannot disclose it publicly here. You "may" directly send e-mail to hardware vendor
telling that you want to help Linux driver.

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i also think so you have the NDA. i tried to figure out what you did in the codes, however, i do not understand why you did a
do_div (t, 30400);
where is the 30400 come from ?

ps. without the spec, we all can do is "test" your code but can not do any suggestion.

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原帖由 chancho 於 2009-11-24 15:35 發表
i also think so you have the NDA. i tried to figure out what you did in the codes, however, i do not understand why you did a
do_div (t, 30400);
where is the 30400 come from ?


The reference clock is 30.4MHz, and the reference design use 30.4MHz too.
If there is some future hardware using difference crystal clock, one have to tell
the ratio(to 30.4MHz) to the register.

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小試左一下, 似乎LOCK 到, 不過都係唔得

$ dvbtune -f 586000
Using DVB card "AltoBeam ATBM8830/8831 DMB-TH"
tuning DVB-T (in United Kingdom) to 586000000 Hz
polling....
Getting frontend event
FE_STATUS:
polling....
Getting frontend event
FE_STATUS: FE_HAS_SIGNAL FE_HAS_LOCK FE_HAS_CARRIER FE_HAS_VITERBI FE_HAS_SYNC
Event:  Frequency: 586000000
        SymbolRate: 0
        FEC_inner:  9
Bit error rate: 0
Signal strength: 59584
SNR: 0
FE_STATUS: FE_HAS_SIGNAL FE_HAS_LOCK FE_HAS_CARRIER FE_HAS_VITERBI FE_HAS_SYNC

$ dvbsnoop -s feinfo
dvbsnoop V1.4.50 -- http://dvbsnoop.sourceforge.net/

---------------------------------------------------------
FrontEnd Info...
---------------------------------------------------------

Device: /dev/dvb/adapter0/frontend0

Basic capabilities:
    Name: "AltoBeam ATBM8830/8831 DMB-TH"
    Frontend-type:       OFDM (DVB-T)
    Frequency (min):     474000.000 kHz
    Frequency (max):     780000.000 kHz
    Frequency stepsiz:   10.000 kHz
    Frequency tolerance: 0.000 kHz
    Symbol rate (min):     0.000000 MSym/s
    Symbol rate (max):     0.000000 MSym/s
    Symbol rate tolerance: 0 ppm
    Notifier delay: 0 ms
    Frontend capabilities:
        auto inversion
        FEC AUTO
        QAM AUTO
        auto transmission mode
        auto guard interval

Current parameters:
    Frequency:  586000.000 kHz
    Inversion:  OFF
    Bandwidth:  8 MHz
    Stream code rate (hi prio):  FEC AUTO
    Stream code rate (lo prio):  FEC AUTO
    Modulation:  QAM AUTO
    Transmission mode:  auto
    Guard interval:  auto
    Hierarchy:  none

$ dvbsnoop -s signal
dvbsnoop V1.4.50 -- http://dvbsnoop.sourceforge.net/

---------------------------------------------------------
Transponder/Frequency signal strength statistics...
---------------------------------------------------------
cycle: 1  d_time: 0.001 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 2  d_time: 0.014 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 3  d_time: 0.013 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 4  d_time: 0.009 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 5  d_time: 0.012 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 6  d_time: 0.010 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 7  d_time: 0.010 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 8  d_time: 0.012 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 9  d_time: 0.010 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 10  d_time: 0.010 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 11  d_time: 0.012 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 12  d_time: 0.010 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 13  d_time: 0.009 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 14  d_time: 0.013 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 15  d_time: 0.009 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 16  d_time: 0.012 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 17  d_time: 0.010 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 18  d_time: 0.010 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 19  d_time: 0.010 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 20  d_time: 0.010 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 21  d_time: 0.009 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 22  d_time: 0.010 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 23  d_time: 0.010 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 24  d_time: 0.009 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 25  d_time: 0.010 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 26  d_time: 0.010 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 27  d_time: 0.009 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 28  d_time: 0.011 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 29  d_time: 0.009 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 30  d_time: 0.010 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 31  d_time: 0.010 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 32  d_time: 0.010 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 33  d_time: 0.009 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 34  d_time: 0.010 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 35  d_time: 0.010 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 36  d_time: 0.010 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 37  d_time: 0.009 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 38  d_time: 0.010 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 39  d_time: 0.010 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 40  d_time: 0.011 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 41  d_time: 0.010 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 42  d_time: 0.009 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 43  d_time: 0.010 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 44  d_time: 0.010 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 45  d_time: 0.010 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 46  d_time: 0.011 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 47  d_time: 0.010 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 48  d_time: 0.010 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 49  d_time: 0.009 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]
cycle: 50  d_time: 0.011 s  Sig: 59584  SNR: 0  BER: 0  UBLK: 0  Stat: 0x1f [SIG CARR VIT SYNC LOCK ]

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多少少資料

$ tzap 'J2(TVB)'
using '/dev/dvb/adapter0/frontend0' and '/dev/dvb/adapter0/demux0'
reading channels from file '/home/xxxxxx/.tzap/channels.conf'
tuning to 586000000 Hz
video pid 0x0335, audio pid 0x0000
status 1f | signal e8c0 | snr 0000 | ber 00000000 | unc 00000000 | FE_HAS_LOCK
status 1f | signal e8c0 | snr 0000 | ber 00000000 | unc 00000000 | FE_HAS_LOCK
status 1f | signal e8c0 | snr 0000 | ber 00000000 | unc 00000000 | FE_HAS_LOCK
status 1f | signal e8c0 | snr 0000 | ber 00000000 | unc 00000000 | FE_HAS_LOCK
status 1f | signal e8c0 | snr 0000 | ber 00000000 | unc 00000000 | FE_HAS_LOCK
status 1f | signal e8c0 | snr 0000 | ber 00000000 | unc 00000000 | FE_HAS_LOCK
status 1f | signal e8c0 | snr 0000 | ber 00000000 | unc 00000000 | FE_HAS_LOCK
status 1f | signal e8c0 | snr 0000 | ber 00000000 | unc 00000000 | FE_HAS_LOCK
status 1f | signal e8c0 | snr 0000 | ber 00000000 | unc 00000000 | FE_HAS_LOCK
status 1f | signal e8c0 | snr 0000 | ber 00000000 | unc 00000000 | FE_HAS_LOCK
status 1f | signal e8c0 | snr 0000 | ber 00000000 | unc 00000000 | FE_HAS_LOCK
status 1f | signal e8c0 | snr 0000 | ber 00000000 | unc 00000000 | FE_HAS_LOCK
status 1f | signal e8c0 | snr 0000 | ber 00000000 | unc 00000000 | FE_HAS_LOCK
^C

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