[FW - Anandtech] AMD Radeon RTG 副總突然休假?

dom

http://www.anandtech.com/show/11836/raja-koduri-sabbatical
睇黎 由 Fury 開始到 Polaris 依家 Vega , 望到 AMD Radeon 真係呢........
提早退休啦你

sl110070

回覆 1# dom


    高層無啦啦放大假一定無好嘢

GeneralShepherd

據講佢番黎由頭到尾都係佢操刀既project係Navi...而且佢都係放下假姐, 冇咩特別...

事實上又GCN太爛, 點改都冇用

Stiggy930

睇黎 由 Fury 開始到 Polaris 依家 Vega , 望到 AMD Radeon 真係呢........
提早退休啦你  ...
dom 發表於 2017-9-13 21:25

其實佢個title 係AMD資深副總裁，RTG首席架構師而唔係RTG副總裁。

Stiggy930

據講佢番黎由頭到尾都係佢操刀既project係Navi...而且佢都係放下假姐, 冇咩特別...

事實上又GCN太爛, 點改 ...
GeneralShepherd 發表於 2017-9-13 21:45

其實，NCU/GCN pure math 一啲都唔失禮。係AMD長期無執過ACE(長年Max 4個)，ROP(長年Max 64個)同tessllation units(長年Max 4個)。AMD要執過front end同back end。CU方面應該仲頂到。

例子：

On a brief aside, the number of compute engines has been an unexpectedly interesting point of discussion over the years. Back in 2013 we learned that the then-current iteration of GCN had a maximum compute engine count of 4, which AMD has stuck to ever since, including the new Vega 10.  Which in turn has fostered discussions about scalability in AMD’s designs, and compute/texture-to-ROP ratios.

Talking to AMD’s engineers about the matter, they haven’t taken any steps with Vega to change this. They have made it clear that 4 compute engines is not a fundamental limitation – they know how to build a design with more engines – however to do so would require additional work. In other words, the usual engineering trade-offs apply, with AMD’s engineers focusing on addressing things like HBCC and rasterization as opposed to doing the replumbing necessary for additional compute engines in Vega 10.

http://www.anandtech.com/show/11 ... -64-and-56-review/2

qcmadness

其實，NCU/GCN pure math 一啲都唔失禮。係AMD長期無執過ACE(長年Max 4個)，ROP(長年Max 64個)同tessllat ...
Stiggy930 發表於 2017-9-13 23:03

執得來不如開新架構, 連VLIW4 efficiency都好過GCN

Stiggy930

執得來不如開新架構, 連VLIW4 efficiency都好過GCN
qcmadness 發表於 2017-9-13 23:08

VLIW4個compiler好果時咪好囉，個compiler一寫得唔好或者個shader codes用唔曬四個SP，performance就好難講。睇IA-64就知個compiler幾難寫。就算呢家開新架構都要四、五年後先見到成果。知期內包括Navi都係要靠執ACE，ROP 同 tessellation units。

qcmadness

VLIW4個compiler好果時咪好囉，個compiler一寫得唔好或者個shader codes用唔曬四個SP，performance就好難 ...
Stiggy930 發表於 2017-9-13 23:19

任何架構都可能有咁既情況架啦
但係mixed simple / complex shader processors的確係正野

MobiusONE

睇黎 由 Fury 開始到 Polaris 依家 Vega , 望到 AMD Radeon 真係呢........
提早退休啦你  ...
dom 發表於 2017-9-13 21:25

唔知今次又唔小心趺左D咩
https://youtu.be/eqCo0LTUhsE?t=3m29s

沙盒A

其實，NCU/GCN pure math 一啲都唔失禮。係AMD長期無執過ACE(長年Max 4個)，ROP(長年Max 64個)同tessllat ...
Stiggy930 發表於 2017-9-13 23:03

VEGA加左個D DSBR又primitive shader
效果都唔係好大咁