本帖最後由 Offer 於 2011-11-23 14:01 編輯
希望好快可以睇到你隻VFD再著既相
FL_RST
FL_CE
FL_DATA
FL_CLK
呢4個係係行緊類似SPI既野? ...
skybread 發表於 2011-11-23 00:43 
It is using synchronous serial communication.
Only three wires are required to communicate with the clock (1) RST (Reset), (2) I/O (Data line),and (3) SCLK (Serial clock). |